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A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ______ bits Gate-cs-20161 AnswerT he size of the physical address space of a processor is 2𝑃 bytes. The word length is 2𝑊 bytes. The capacity of cache memory is 2𝑁 bytes. The size of each cache block is 2𝑀 words. For a 𝐾-way set-associative cache memory, the length (in number of bits) of the tag field is1 AnswerThe size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the c1 AnswerConsider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively: -computer science-gate-2001 Answer Assume that the memory is word addressable. After the execution of this program, the content of memory location 20lO is -computer science-gate-20071 AnswerConsider a hypothetical processor with an instruction of type LW R1, 20(R2) -gate-cse-20111 AnswerA computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. -gate-cse-20121 AnswerA computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. -gate-cse-20121 AnswerIn an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?Gate-20161 AnswerConsider the following C declaration GATE CSE 20001 AnswerHow does Node.js support multi-processor platforms, and does it fully utilize all processor resources?1 AnswerConsider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. -gate-cse-20151 AnswerCompare Pentium1,Pentium2 and Pentium3 processor.-Microprocessors-Mumbai University-Sem 5-Dec 2015,Dec 20161 AnswerIn the passage given below, one word has been omitted in each line. Write the missing word along with the word that comes before and the word that comes after it.CBSE-English-20141 AnswerT he following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?1 AnswerLet us assume Data is a two-dimensional array (Computer-Science-2018) 1 AnswerA 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.1 AnswerExplain in detail the architecture support for protecting processes from each other via Virtual Memory.1 AnswerQ.56) A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits. -gate computer science 20171 AnswerB+ -trees are preferred to binary trees in databases because GATE CSE 20001 Answer
Smart Memories report,pptSYSTEM SOFTWARE [10CS52] Unit-1Advance Computer Architecture [10CS74] unit-6Handheld ComputersIntelligent RAM Intel Centrino Mobile TechnologyAdvance Computer Architecture [10CS74] unit-7SYSTEM SOFTWARE [10CS52] Unit-2ADVANCED COMPUTER ARCHITECTURES 10CS74 Embedded Systems and Information Appliances
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