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Logic-Design---10CS33-VTU-notes10CS33-->View question


Asked On2017-05-15 09:26:22 by:pallaviaithaln

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The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a clock input.
Truth table:
same as
for the
SR Latch
InputOutputDescription
JKQQ
0000Memory
no change
0001
0110Reset Q » 0
0101
1001Set Q » 1
1010
toggle
action
1101Toggle
1110


Answerd on:2017-06-06 Answerd By:prajwalamv

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