Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU we can say thatGATE CSE 2000

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Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that?GATE CSE 2000

A=T1 <= T2
B=T1 >= T2
C=T1 < T2
D=T1 is T2 plus the time taken for one instruction fetch cycle


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(B) T1 >= T2 Pipelining does not increase the execution time of a single instruction. It increases the overall performance by executing instructions in multiple pipeline stages. We assume that each stage takes ‘T’ unit of time both in pipelined and non-pipelined CPU. Let total stages in pipelined CPU = Total stages in non-pipelined CPU = K and number of Instructions = N = 1 Pipelined CPU : Total time (T1) = (K + (N – 1)) * T = KT Non-Pipelined CPU : Total time (T2) = KNT = KT Considering buffer delays in pipelined CPU, T1 >= T2 Thus, option (B) is the answer.

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