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A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. -gate-cse-2012

The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is
A.11
B.14
C.16
D.27


Asked On2017-07-03 08:17:48 by:prajwalamv

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(C) 16
Explanation: A set-associative scheme is a hybrid between a fully associative cache, and direct mapped cache. It’s considered a reasonable compromise between the complex hardware needed for fully associative caches (which requires parallel searches of all slots), and the simplistic direct-mapped scheme, which may cause collisions of addresses to the same slot (similar to collisions in a hash table). 

Answerd on:2017-07-04 Answerd By:milan-ransingh

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