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Explain the diferent instruction formats in 8086 micro processor1 AnswerExplain direction flag and auxiliary flags of 8086 micro processors2 AnswerDiscuss the functions of DT/R pins in 8086 micro processor IC1 AnswerWhat changes does xchg instruction do to the content of the 2 registers?1 AnswerWhat changes does lahf and sahf instruction do to the content of the 2 registers?1 AnswerDiscuss the functions of ALE and AD0 TO AD15 pins in 8086 microprocessor IC1 AnswerQ.65) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns . -gate computer science 20171 AnswerWhat is the bus arbiter in micro processor?1 AnswerExplain flag registers of 8086 microprocessors.1 AnswerConsider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. -gate-cse-20151 AnswerT he following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?1 AnswerExplain direct addressing input output ports.1 AnswerExplain how to write a assembly level program to generating fibonacci series.1 AnswerWhat does MOV AX,[BX+08H] mean in micro processor?1 AnswerT he instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions is ______.1 AnswerWrite-a-note-on-e-business-and-accounting/11 AnswerC onsider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?1 AnswerWhat is a decoder table?1 AnswerList the differences between Micro processor and Micro controller. 1 AnswerHow are multiplexers used is networking and server systems?1 Answer
10ec62 Micro processor06cs45 MicroProcessorSYSTEM SOFTWARE [10CS52] Unit-1 Intel Centrino Mobile Technology06csl48 micro processor lab manualIntroduction to Microprocessors - CSE45 VTU notes8086 Microprocessor & Peripherals - 06IT/BM 52 VTU notesMoto GSYSTEM SOFTWARE [10CS52] Unit-6Model Question Paper PROGRAMMING IN C AND DATA STRUCTURES (14PCD13/14PCD23)
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