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The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.
Processor vs system on chip
Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is M units if the corresponding memory page is available in memory, and D units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory access in the process is X units.
In an orthogonal machining with a single point cutting tool of rake angle 10°, the uncut chip thickness and the chip thickness are 0.125 mm and 0.22 mm, respectively. Using Merchant’s first solution for the condition of minimum cutting force, the coefficient of friction at the chip-tool interface is ______ (round off to two decimal places).
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is __________× 10^6 bytes/sec.
computer organization and architecture
A floppy disk is ?
In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?Gate-2016
Write notes on buddy system of memory management in unix?
You are the head of a Mutual Fund responsible for the investing fund in different ways. Fromthemarket trends you find that blue-chip companies and government securities will generally not do as well as corporate bonds in the coming year. However government regulations require that at least one-third of your Mutual Funds capital must be in blue- chip stocks and another third in corporate bonds. If the return on government securities suddenly goes up by five percent, you will probably
F ollowing data correspond to an orthogonal turning of a 100 mm diameter rod on a lathe. Rake angle: o15 ; Uncut chip thickness: 0.5 mm; nominal chip thickness after the cut: 1.25 mm. The shear angle (in degrees) for this process is _______ (correct to two decimal places).
Consider the virtual page reference string 1, 2, 3, 2, 4, 1, 3, 2, 4, 1 -gate-cse-2012
Assume that the memory is word addressable. After the execution of this program, the content of memory location 20lO is -computer science-gate-2007
Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressible. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?
Explain memory system mechanisms? Jan 14?
Consider a hypothetical processor with an instruction of type LW R1, 20(R2) -gate-cse-2011
In an orthogonal machining with a tool of 9° orthogonal rake angle, the uncut chip thickness is 0.2mm. The chip thickness fluctuates between 0.25 mm and 0.4 mm. The ratio of the maximum shear angel to the minimum shear angle during machining is _________
What is system call.Explain the types of system call.
A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ______ bits Gate-cs-2016