This is designed to incentify community members as a proof of contribution token.

Using this You can,Buy courses,Reward others and exchange for real money.

WHITE PAPER COURSES

Real Problems! Real Experts!

Join Our Telegram Channel !

In eduladder you can Ask,Answer,Listen,Earn and Download Questions and Question papers.

Watch related videos of your favorite subject.

Connect with students from different parts of the world.

Apply or Post Jobs, Courses ,Internships and Volunteering opportunity. For FREE

See Our team

Wondering how we keep quality?

Got unsolved questions? Ask Questions

GATE
GMAT
CBSE
NCERT
Career
Interview
Railway
UPSC
NID
NIFT-UG
NIFT-PG
PHP
AJAX
JavaScript
Node Js
Shell Script
Research

Checkout our YouTube channel for video tutorials and learn more about Eduladder.

New updates

Updated ProfileDate:2022-09-29 05:16:46Done by:kirakgouldSearching for :Fault masking isDate:2022-09-29 05:08:39Done by:Anonymous user(Visitor)

Searching for :Fault masking isDate:2022-09-29 05:08:33Done by:Anonymous user(Visitor)

View All

Career 2.0

You might be intrested on below oppertunities Show me All

### Similar Questions

**An n-channel FET having Gate-Source switch-off voltage VGS(OFF) = – 2 V is used to invert a 0 – 5 V square-wave signal as shown. The maximum allowed value of R would be ________ k (up to two decimal places).**

0 Answer

**The channel resistance of an N-channel JFET shown in the figure below is 600 Ω -gate-ece-2011**

1 Answer

**The channel resistance of an N-channel JFET shown in the figure below is 600 Ω -gate-ece-2011**

1 Answer

**Consider a long-channel MOSFET with a channel length 1 μm and width 10 μm. The device parameters are acceptor concentration NA= 5 × 1016 cm-3 , electron mobility μn=800 cm2 /V-s, oxide capacitance/area Cox= 3.45 × 10−7 F/cm2 , threshold voltage VT=0.7 V. The drain saturation current (IDsat) for a gate voltage of 5 V is _____mA (rounded off to two decimal places). [ε0 = 8.854 × 10−14F/cm, εSi = 11.9]**

1 Answer

**The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. -GATE EC 2015**

1 Answer

**In the circuit shown, Vs is a 10 V square wave of period, T = 4 ms with R = 500 Ω and C = 10 μF. The capacitor is initially uncharged at t=0, and the diode is assumed to be ideal. The voltage across the capacitor (Vc ) at 3 ms is equal to ____ volts (rounded off to one decimal place).**

1 Answer

**In the circuit shown, Vs is a square wave of period T with maximum and minimum values of 8 V and -10 V, respectively. Assume that the diode is ideal and R1 = R2 = 50 Ω. The average value of VL is ____ volts (rounded off to 1 decimal place).**

1 Answer

**The baseband signal m(t) shown in the figure is phase-modulated to generate the PM signal φ(t) = cos(2πfc t + k m(t)). The time t on the x-axis in the figure is in milliseconds. If the carrier frequency is fc = 50 kHz and k = 10π, then the ratio of the minimum instantaneous frequency (in kHz) to the maximum instantaneous frequency (in kHz) is __________ (rounded off to 2 decimal places).**

0 Answer

**A carrier wave of peak voltage 15 V is used to transmit a message signal. Find the peak voltage of the modulating signal in order to have a modulation index of 60%. (Physics CBSE 2018)**

1 Answer

**The RC circuit shown below has a variable resistance R(t) given by the following expression: R(t) = R0 (1 − t/T ) for 0 ≤ t < T where R0 = 1 Ω, and C = 1 F. We are also given that T = 3 R0C and the source voltage is Vs = 1 V. If the current at time t = 0 is 1 A, then the current I(t), in amperes, at time t = T/2 is ___________ (rounded off to 2 decimal places).**

0 Answer

**In the circuit shown below, the initial charge on the capacitor is 2.5 mC -gate-ece-2011**

1 Answer

**In the system shown in figure (a), m(t) is a low-pass signal with bandwidth W Hz. -GATE EC 2015**

1 Answer

**Fill in the blanks GATE-Instrumentation-Engineering-2014**

1 Answer

**The slope of a channel in alluvium is 14000 Laceys silt factor is 09 and side slopes are 12H 1V .Find the channel section and maximum discharge which can be allowed to flow in it.**

0 Answer

**The enhancement type MOSFET in the circuit below operates according to the square law. μnCox = 100 μA/V 2 , the threshold voltage (VT) is 500 mV. Ignore channel length modulation. The output voltage Vout is:**

1 Answer

**Given, Vgs is the gate-source voltage, Vds is the drain source voltage, and Vth is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are (A) Vgs < Vth ; Vds ≥ Vgs − Vth (B) Vgs > Vth ; Vds ≥ Vgs − Vth (C) Vgs > Vth ; Vds ≤ Vgs − Vth (D) Vgs < Vth ; Vds ≤ Vgs − Vth**

1 Answer

**the maximum power dissipation in Q1 (in Watts) is _____________. -GATE EC 2015**

1 Answer

**A solar cell of area 2 1.0 cm , operating at 1.0 sun intensity, has a short circuit current of 20 mA, and an open circuit voltage of 0.65 V. Assuming room temperature operation and thermal equivalent voltage of 26mV, the open circuit voltage (in volts, correct to two decimal places) at 0.2 sun intensity is _______.**

1 Answer

**A circular steel bar of diameter 10 mm is bent into the shape as shown in figure, and lies in x-z plane. A horizontal force P is applied along the positive z-direction as shown. The yield strength of the steel is 200 MPa. Neglecting the effect of transverse shear, the load P (in Newton) required to initiate yielding as per maximum shear stress theory of failure is............[up to two decimal places]**

0 Answer

**The output voltage of a single-phase full bridge voltage source inverter is controlled by unipolar PWM with one pulse per half cycle. For the fundamental rms component of output voltage to be 75% of DC voltage, the required pulse width in degrees (round off up to one decimal place) is __________.**

1 Answer

### Notes

**Laser Communications**

**GE6252 Basic Electrical and Electronics Engineering Anna university notes**

**brain computer interface**

**Digital Light Processing**

**Low Energy Efficient Wireless Communication Network Design**

**COMPUTER NETWORKS I[10CS55] unit-2**

**EE2151 CIRCUIT THEORY**

**ieee 802.22 wran**

**ABB PAPER - 02 MAY 2004 - VADODARA**

**CE 2030 COASTAL ZONE MANAGEMENT**

## An n-channel FET having Gate-Source switch-off voltage VGS(OFF) = – 2 V is used to invert a 0 – 5 V square-wave signal as shown. The maximum allowed value of R would be ________ k (up to two decimal places).

## Gate Physics

Asked On2019-04-09 05:00:08 by:Rohit498

Taged users:

Likes:

Rohit498

Dislikes:

Be first to dislike this question

Talk about this Like Dislike

Download question setAnswersNot yet answerdThis question has not found any answer yet! If you know the answer for this question please help us to find an answer.Please read

How to post an answer on eduladder

Lets together make the web is a better placeWe made eduladder by keeping the ideology of building a supermarket of all the educational material available under one roof. We are doing it with the help of individual contributors like you, interns and employees. So the resources you are looking for can be easily available and accessible also with the freedom of remix reuse and reshare our content under the terms of creative commons license with attribution required close.

You can also contribute to our vision of "Helping student to pass any exams"with these.Answer a question:You can answer the questions not yet answered in eduladder.How to answer a questionCareer:Work or do your internship with us.Work with usCreate a video:You can teach anything and everything each video should be less than five minutes should cover the idea less than five min.How to upload a video on eduladder