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Advance-Computer-Architecture-10CS74-unit-6-->View question

Q.65) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns . -gate computer science 2017

Two pipelined implementations of the processor are contemplated: 
(i) a na├»ve pipeline implementation (NP) with 5 stages and 
(ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively. 

The speedup (correct to two decimals places) achieved by EP over NP in executing 20 independent instructions with no hazards is ________________. 

A) 1.50-1.51
B) 1.51-1.52
C) 1.52-1.53
D) 1.53-1.54


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A) 1.50-1.51

Explanation :-
Given, total number of instructions (n) = 20 
For naive pipeline (NP):
Number of stages(k) = 5
Clock time (Tp) = max { (stage delay+buffer delay) } = { 7, 6, 22, 12, 5 } = 22 nsec
Execution time (Enp) = ( k + n - 1 )*Tp = ( 5 + 20 - 1 )*22 = 528 nsec
For efficient pipeline (EP):
number of stages(k) = 6 ( delay with 20 nsec stage is divided into 12 nsec and 8 nsec )
Clock time (Tp) = max { (stage delay+buffer delay) } = { 7, 6, 14, 10, 14, 5 } = 14 nsec
Execution time (Eep) =  ( k + n - 1 )*Tp = ( 6 + 20 - 1 )*14 = 350 nsec
Therefore, Speedup = (Enp) / (Eep) = 528 / 350 = 1.508 

This explanation is contributed by Satya Shiromani


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