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Define-Amdahls-law--Derive-an-expression-for-CPU-clock-as-a-function-of-instruction-count-clocks-per-instruction-and-clock-cycle-time/11 AnswerDefine Amdahls law. Derive an expression for CPU clock as a function of instruction count clocks per instruction and clock cycle time.1 AnswerThe clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is -gate Electronics and Communication 20171 AnswerComparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that?GATE CSE 20001 AnswerAssume we have a computer where the clock per instruction(CPI) i s 1 . 0 when all memory accesses hit the cache . the only data accesses are loads and stores and these total 50 % of the instructions . if the mass penality is 25 clock cycles and the m1 AnswerConsider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. -gate-cse-20151 AnswerConsider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________.1 Answerlf at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge? -gate-computer science-20111 AnswerExplain the 8085 instruction set.1 AnswerWith 12 MHz clock frequency how many instructions (of 1 machine cycle and 2 machine cycle) it can execute per second?1 AnswerIn an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?Gate-20161 AnswerWhich type of cycle is used for fetch and execute instruction?1 AnswerExplain Digital clock with block Diagram1 AnswerQ.65) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns . -gate computer science 20171 AnswerExpress as 24- hours clock time-CBSE-Mathematics-Class 41 AnswerConsider a hypothetical processor with an instruction of type LW R1, 20(R2) -gate-cse-20111 AnswerThe 8085 microprocessor responds to the presence of an interrupt -GATE CSE 20001 Answer Explain principle of moments. Derive its expression for a lever. -Physics Cbse class 11 1 AnswerWhat is clock speed?1 AnswerWhat is the Maximum clock frequency in 8086?1 Answer