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Q.65) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns . -gate computer science 20171 AnswerT he instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions is ______.1 AnswerConsider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. -gate-cse-20151 AnswerConsider a hypothetical processor with an instruction of type LW R1, 20(R2) -gate-cse-20111 AnswerT he following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?1 AnswerComparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that?GATE CSE 20001 AnswerExplain the diferent instruction formats in 8086 micro processor1 AnswerWe split testing into distinct stages primarily because1 AnswerWhat changes does xchg instruction do to the content of the 2 registers?1 AnswerWhat changes does lahf and sahf instruction do to the content of the 2 registers?1 AnswerThe clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is -gate Electronics and Communication 20171 AnswerC onsider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?1 AnswerExplain the 8085 instruction set.1 AnswerWhat are the steps that are taken to decode an instruction code?1 AnswerDefine-Amdahls-law--Derive-an-expression-for-CPU-clock-as-a-function-of-instruction-count-clocks-per-instruction-and-clock-cycle-time/11 AnswerThe 8085 microprocessor responds to the presence of an interrupt -GATE CSE 20001 AnswerIn an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?Gate-20161 AnswerDefine Amdahls law. Derive an expression for CPU clock as a function of instruction count clocks per instruction and clock cycle time.1 Answercomputer organization 1 AnswerConsider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________. -gate computer science 20171 Answer
Advance Computer Architecture [10CS74] unit-2Advance Computer Architecture [10CS74] unit-4Advance Computer Architecture [10CS74] unit-6ADVANCED COMPUTER ARCHITECTURES 10CS74 SYSTEM SOFTWARE [10CS52] Unit-1Advance Computer Architecture [10CS74] unit-3SYSTEM SOFTWARE [10CS52] Unit-210ec62 Micro processorAdvance Computer Architecture [10CS74] unit-806cs45 MicroProcessor
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