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Q.56) A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits. -gate computer science 20171 AnswerA computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. -gate-cse-20121 AnswerA computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. -gate-cse-20121 AnswerQ.50) Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. Conflict misses are those misses which occur due the contention of multiple blocks for the same cache set. -gate computer science 20171 AnswerConsider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively: -computer science-gate-2001 AnswerConsider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________. -gate computer science 20171 AnswerWrite two advantages and disadvantages of Cache memory. CBSE CLASS VI-20161 AnswerExplain the types of basic cache optimization .1 AnswerExplain in brief ,the types of basic cache optimisation ?1 AnswerThe size of the cache tag directory is -gate-computer science-20121 AnswerWith a diagram, explain organization of data cache in the Microprocessor.1 AnswerExplain the directory based cache coherence for a distributed memory multiprocessor system along with state transition diagram?1 AnswerExplain the following advanced optimization of cache 1 Compiler optimizations to reduce miss rate 2 Merging write buffer to reduce miss penalty 3 Non blocking cache to increase cache band width.1 AnswerWhich are the major categories of the advanced optimization o f cache performance? explain any one in details?1 AnswerWhat is cache memory?1 AnswerWhen two 8-bit numbers A7 ... A0 and B7 ... B0 in 2s complement representation (with A0 and B0 as the least significant bits) are added using ripple-carry adder. the sum bits obtained are S7 ... S0 and the carry bits are C7 ... C0. An overflow is said to have occured if : -gate computer science 20171 AnswerWhen two 8-bit numbers A7 ... A0 and B7 ... B0 in 2s complement representation (with A0 and B0 as the least significant bits) are added using ripple-carry adder. the sum bits obtained are S7 ... S0 and the carry bits are C7 ... C0. An overflow is said to have occured if : -gate computer science 20171 AnswerConsider two binary operators uparrow and downarrow . -gate-cse-20111 AnswerWhich of the following has highest level of independence in which test cases are :0 AnswerExplain block replacement strategies to replace a block, with example when a cache?1 Answer