Consider the D Latch shown in the figure which is transparent when its clock input CK is high and has zero propagation delay In the figure the clock signal CLK1 has a 50 duty cycle and CLK2 is a one fifth period delayed version of CLK1 The duty cycle at the output latch in percentage is

The Eduladder is a community of students, teachers, and programmers just interested to make you pass any exams. So we solve previous year question papers for you.
See Our team
Wondering how we keep quality?
Got unsolved questions?

Ask Questions
GATE-Electronics-and-Communication-Engineering-Question-Paper-2013-download-->View question


Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________.




By:aksingh1818

Taged users:
|aksingh1818|Abhishek|deepuckraj|Jessika-K|ahmed-elgohary|satyashiromani|Shikhil|Purnima|13priya|RahulR|naveen-kumar-m|Razeen-raaz|sucharitha-d||Aparna-Dasgupta|rathinlz04|Akhil-Raj|maverick-ashwin|Ravi-gowda|arunwebber|eduladder|Abdul-Wajid|neenu2|Johnny|salazar|ratika|pallaviaithaln|Raju-bhai|Asgar-Ali|Aditya-Kashyap

Likes:
Be first to like this question

Dislikes:
Be first to dislike this question

Talk about thisDelete|Like|Dislike|


Answers

                                                                                                                                                                                        
             



Sai-kiran

Likes:
|Sai-kiran

Dislikes:
Be first to dislike this answer
Talk about this|Once you have earned teacher badge you can edit this questionDelete|Like|Dislike|
------------------------------------

Can you help us to add better answer here? Please see this



Not the answer you're looking for? Browse other questions from this Question paper or ask your own question.

Join eduladder!