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A) 0.05

Explanation:  
Let 1000 instructions generated 121 Therefore, Miss rate of L2 cache = (memory references generated by L2 cache) / (memory references generated by L1 cache) = 7 / 140 = 0.05 Alternate Solution 

On Average, 1.4 memory accesses are required for one instruction execution. 
So, for 1000 instructions, 1400 accesses are needed. 
Number of misses occurred in cache L2 for 1000 instruction = 7/1400 = 0.005 
Miss rate of L2 cache = misses occured in L2 cache / miss rate in L1 cache 
= 0.005 / 0.1 = 0.05 (A)

Answerd on:2018-05-30 Answerd By:deepuckraj

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