Explain interrupt structure of 8086

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Explain interrupt structure of 8086.

Related to 8086 microprocessor.


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Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.

It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these actions take place −

Completes the current instruction that is in progress.

Pushes the Flag register values on to the stack.

Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.

IP is loaded from the contents of the word location 00008H.

CS is loaded from the contents of the next word location 0000AH.

Interrupt flag and trap flag are reset to 0.

The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller.

These actions are taken by the microprocessor −

First completes the current instruction.

Activates INTA output and receives the interrupt type, say X.

Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack.

IP value is loaded from the contents of word location X × 4

CS is loaded from the contents of the next word location.

Interrupt flag and trap flag is reset to 0



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