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You are here:Open notes-->VTU-->Logic-Design---10CS33-VTU-notes10CS33

Logic Design - 10CS33 VTU notes(10CS33)

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                                                  LOGIC DESIGN
(Common to CSE & ISE)
Subject Code: 10CS33
Hours/Week : 04
Total Hours : 52
I.A. Marks : 25
Exam Hours: 03
Exam Marks: 100
UNIT – 1
7 Hours
Digital Principles, Digital Logic: Definitions for Digital Signals, Digital
Waveforms, Digital Logic, 7400 TTL Series, TTL Parameters The Basic
Gates: NOT, OR, AND, Universal Logic Gates: NOR, NAND, Positive and
Negative Logic, Introduction to HDL.
UNIT – 2
6 Hours
Combinational Logic Circuits
Sum-of-Products Method, Truth Table to Karnaugh Map, Pairs Quads, and
Octets, Karnaugh Simplifications, Don’t-care Conditions, Product-of-sums
Method, Product-of-sums simplifications, Simplification by Quine-McClusky
Method, Hazards and Hazard Covers, HDL Implementation Models.
UNIT – 3
6 Hours
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder,
Encoders, Exclusive-or Gates, Parity Generators and Checkers, Magnitude
Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL
Implementation of Data Processing Circuits

UNIT – 4
7 Hours
Clocks, Flip-Flops: Clock Waveforms, TTL Clock, Schmitt Trigger,
Clocked D FLIP-FLOP, Edge-triggered D FLIP-FLOP, Edge-triggered JK
FLIP-FLOP, FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch
Contact Bounce Circuits, Various Representation of FLIP-FLOPs, Analysis
of Sequential Circuits, HDL Implementation of FLIP-FLOP


UNIT – 5
6 Hours
Registers: Types of Registers, Serial In - Serial Out, Serial In - Parallel out,
Parallel In - Serial Out, Parallel In - Parallel Out, Universal Shift Register,
Applications of Shift Registers, Register Implementation in HDL
UNIT – 6
7 Hours
Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters,
Changing the Counter Modulus, Decade Counters, Presettable Counters,
Counter Design as a Synthesis problem, A Digital Clock, Counter Design
using HDL
UNIT – 7
7 Hours
Design of Synchronous and Asynchronous Sequential Circuits: Design of
Synchronous Sequential Circuit: Model Selection, State Transition Diagram,
State Synthesis Table, Design Equations and Circuit Diagram,
Implementation using Read Only Memory, Algorithmic State Machine, State
Reduction Technique.
Asynchronous Sequential Circuit: Analysis of Asynchronous Sequential
Circuit, Problems with Asynchronous Sequential Circuits, Design of
Asynchronous Sequential Circuit, FSM Implementation in HDL
UNIT – 8
6 Hours
D/A Conversion and A/D Conversion: Variable, Resistor Networks, Binary
Ladders, D/A Converters, D/A Accuracy and Resolution, A/D Converter-
Simultaneous Conversion, A/D Converter-Counter Method, Continuous A/D
Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy
and Resolution

Text Book:
1. Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital
Principles and Applications, 7 th Edition, Tata McGraw Hill, 2010.
Reference Books:
1. Stephen Brown, Zvonko Vranesic: Fundamentals of Digital Logic
Design with VHDL, 2 nd Edition, Tata McGraw Hill, 2005.
2. R D Sudhaker Samuel: Illustrative Approach to Logic Design,
Sanguine-Pearson, 2010.
3. Charles H. Roth: Fundamentals of Logic Design, Jr., 5 th Edition,
Cengage Learning, 2004.
4. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss: Digital Systems
Principles and Applications, 10 th Edition, Pearson Education, 2007.
5. M Morris Mano: Digital Logic and Computer Design, 10 th Edition,
Pearson Education, 2008.

Official Notes

Logic Design - 10CS33
e-NotesTopicSubject Matter Experts
Registers, Counters, Design of Synchronous and Asynchronous Sequential Circuits, D/A Conversion and A/D Conversion
Dr.Sahana D Gowda, BNMIT, B'lore
Digital Principles, Digital Logic, Combinational Logic Circuits, Data Processing Circuits, Clocks, Flip-Flops
Prof.B.S.Umashankar, BNMIT, B'lore

Notes from other source

Unit I

Unit II

Unit III

Unit IV

Unit V

Model question papers


Previous year question papers

May june 2010

june july 2011

Dec 2010

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