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You are here:Open notes-->Seminar-topics-and-ppt-for-engineering-->Green-droid

Green droid

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The GreenDroid mobile application processor is a 45-nm multicore research prototype that targets the Android mobile-phone software stack and can execute general-purpose mobile programs with 11 times less energy than todayís most energy-efficient designs, at similar or better performance levels. It does this through the use of a hundred or so automatically generated, highly specialized, energy-reducing cores, called conservation cores. Our research attacks a key technological problem for microprocessor architects, which we call the utilization wall. 1 The utilization wall says that, with each process generation, the percentage of transistors that a chip design can switch at full frequency drops exponentially because of power constraints. A direct consequence of this is dark siliconólarge swaths of a chipís silicon area that must remain mostly passive to stay within the chipís power budget. Currently, only about 1 percent of a modest-sized 32-nm mobile chip can switch at full frequency within a 3-W power budget. With each process generation, dark silicon gets exponentially cheaper, whereas the power budget is becoming exponentially more valuable. Our research leverages two key insights. First, it makes sense to find architectural techniques that trade this cheap resource, dark silicon, for the more valuable resource, energy efficiency. Second, specialized logic can attain 10x to 1000x better energy efficiency over general-purpose processors. Our approach is to fill a chipís dark silicon area with specialized cores to save energy on common applications. These cores are automatically generated from the code base that the processor is intended to runóthat is, the Android mobile-phone software stack. The cores feature a focused reconfigurability so that they can remain useful even as the code they target evolves.

The Utilization Wall

Although Mooreís law continues to offer exponential increases in transistor countó especially with the promise of 3D integrationóCMOS scaling has broken down. We refer to CMOS scaling as the scaling of transistor properties as set down by Dennard in his 1974 paper.2 It is this breakdown of CMOS scaling that led to the industrial shift from single-threaded to multicore processors around 2005. (The ĎĎUnderstanding the Origins of the Utilization Wallíí sidebar explains this breakdown in greater detail.) Although a fixed-size chipís computing capabilities continue to increase exponentially at 2.8. The utilization wall problem is already apparent indirectly through the product lines of major processor manufacturers. Processor frequencies havenít increased for almost half a decade, and the number of cores on a chip hasnít been scaling at the same rate as the increase in the number of transistors. An increasing percentage of each chip is being dedicated to cache or lowactivity logic such as memory controllers and portions of the processorís chipset. Recently, Intelís Nehalem architecture has featured a Turbo Boost mode that runs some cores faster if the others are switched off. All of these observations show that the utilization wall is strongly shaping the evolution of processor designs. CMOS scaling theory indicates that things are going to get exponentially worse. Future architectures that try to maximize the benefit due to new process generations will need to be consciously designed to leverage many, many transistors, in a way that uses only a tiny fraction of them at a time. GreenDroidís conservation cores have these exact properties and can be used to relax the utilization wallís extreme power constraints.

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