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Subject Code: 10CS846 I.A. Marks : 25 Hours/Week : 04 Exam Hours: 03 Total Hours : 52 Exam Marks: 100 PART - A
UNIT 1 7 Hours
Introduction The power and potential of parallelism, Examining sequential and parallel programs, Parallelism using multiple instruction streams, The Goals: Scalability and performance portability, Balancing machine specifics with portability, A look at six parallel computers: Chip multiprocessors, Symmetric multiprocessor architectures, Heterogeneous chip designs, Clusters, Supercomputers, Observations from the six parallel computers. UNIT 2 6 Hours
Reasoning about Performance Motivation and basic concepts, Sources of performance loss, Parallel structure, Performance trade-offs, Measuring performance, Scalable performance.
UNIT 3 6 Hours
Examples of Multi-Core Architectures Introduction to Intel Architecture, How an Intel Architecture System works, Basic Components of the Intel Core 2 Duo Processor: The CPU, Memory Controller, I/O Controller; Intel Core i7: Architecture, The Intel Core i7 Processor, Intel QuickPath Interconnect, The SCH; Intel Atom Architecture. 125 Introduction to Texas Instruments’ Multi-Core Multilayer SoC architecture for communications, infrastructure equipment
UNIT 4 7 Hours
Parallel Algorithm Design Introduction, The Task / Channel model, Foster’s design methodology, Examples: Boundary value problem, Finding the maximum, The n-Body problem, Adding data input. PART – B

UNIT 5 7 Hours
Parallel Programming – 1 (Using OpenMP) Designing for threads: Task decomposition, Data decomposition, Data flow decomposition, Implications of different decompositions; Challenges in decomposition, Parallel programming patters, A motivating problem: Error diffusion. Threading and Parallel Programming Constructs: Synchronization, Critical sections, Deadlocks, Synchronization primitives: Semaphores, Locks, Condition variables; Messages, Flow Control-Based concepts: Fence, Barrier; Implementation-Dependent threading issues.
UNIT 6 6 Hours
Parallel Programming – 2 (Using OpenMP) Introduction, The shared-memory model, Parallel for loops, Declaring private variables, Critical sections, Reductions, Performance improvements, More general data parallelism, Functional parallelism.

UNIT 7 7 Hours
Solutions to Common Parallel Programming Problems Too many threads, Data races, deadlocks, and live locks, Heavily contended locks, Non-blocking algorithms, Thread-safe functions and libraries, Memory issues, Cache-related issues, Avoiding pipeline stalls, Data organization for high performance.
UNIT 8 6 Hours
Threading in the Processor Single-Core Processors: Processor architecture fundamentals, Comparing Superscalar and EPIC architectures. Multi-Core Processors: Hardware-based threading, Hyper-threading technology, Multi-Core processors, Multiple processor interactions, Power consumption, Beyond multi-core architecture. NOTE: In order to acquire a sound understanding of the subject, it is desirable for the students to work in the laboratory using OpenMP. The 126 hands-on experience would reinforce the concepts learnt in theory. Problems similar to the ones solved in the Algorithms Laboratory can be solved and issues like speed-up achieved can be analyzed in depth. Several free tools are available from companies like INTEL to facilitate such a study.

Text Books:

1. Calvin Lin, Lawrence Snyder: Principles of Parallel Programming, Pearson Education, 2009. (Listed topics only from Chapters 1, 2, 3) 2. Michael J. Quinn: Parallel Programming in C with MPI and OpenMP, Tata McGraw Hill, 2004. (Listed topics only from Chapters 3, 17) 3. Shameem Akhter, Jason Roberts: Multi-Core Programming, Increasing Performance through Software Multithreading, Intel Press, 2006. (Listed topics only from Chapters 3, 4, 7, 9, 10) 4. Web resources for Example Architectures of INTEL and Texas Instruments: http://download.intel.com/design/intarch/papers/321087.pdf ; http://focus.ti.com/lit/wp/spry133/spry133.pdf Reference Books: 1. Introduction to Parallel Computing – Ananth Grama et. al., Pearson Education, 2009. 2. Reinders : Intel Threading Building Blocks, O’reilly – 2005 3. David Culler et. al.: Parallel Computer Architecture: A Hardware/Software Approach, Elsevier, 2006. 4. Richard Gerber, Aart J.C. Bik, Kevin B. Smith, Xinmin Tian: Software Optimization Cookbook, High-Performance Recipes for IA-32 Platforms, 2nd Edition, Intel Press, 2006. 

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