View note:Advance-Computer-Architecture-10CS74-unit-6

Questions of this subject!.

1)How to avoid address translation during indexing of the cache to reduce hit time?

2)Differentiate between memory mapped i/o and i/o mapped i/o

3)What is IP address?

4)Briefly explain any two of the cache mapping functions

5)Write two advantages and disadvantages of Cache memory. CBSE CLASS VI-2016

6)Q.65) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns . -gate computer science 2017

7)T he size of the physical address space of a processor is 2𝑃 bytes. The word length is 2𝑊 bytes. The capacity of cache memory is 2𝑁 bytes. The size of each cache block is 2𝑀 words. For a 𝐾-way set-associative cache memory, the length (in number of bits) of the tag field is

8)What are the drawbacks of associate mapping? Explain how to overcome drawbacks of associative mapping in cache memory

9)Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is M units if the corresponding memory page is available in memory, and D units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory access in the process is X units.

10)Increasing the RAM of a computer typically improves performance because: (a) Virtual memory increases (b) Larger RAMs are faster (c) Fewer page faults occur (d) Fewer segmentation faults occur