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Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. -gate-cse-20151 AnswerQ.65) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns . -gate computer science 20171 AnswerComparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that?GATE CSE 20001 AnswerIn an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?Gate-20161 AnswerConsider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________. -gate computer science 20171 AnswerDefine-Amdahls-law--Derive-an-expression-for-CPU-clock-as-a-function-of-instruction-count-clocks-per-instruction-and-clock-cycle-time/11 AnswerAssume we have a computer where the clock per instruction(CPI) i s 1 . 0 when all memory accesses hit the cache . the only data accesses are loads and stores and these total 50 % of the instructions . if the mass penality is 25 clock cycles and the m1 AnswerThe clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is -gate Electronics and Communication 20171 AnswerDefine Amdahls law. Derive an expression for CPU clock as a function of instruction count clocks per instruction and clock cycle time.1 AnswerThe following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),GATE CSE 20001 AnswerExplain the diferent instruction formats in 8086 micro processor1 AnswerConsider a hypothetical processor with an instruction of type LW R1, 20(R2) -gate-cse-20111 AnswerWhat changes does xchg instruction do to the content of the 2 registers?1 AnswerWhat changes does lahf and sahf instruction do to the content of the 2 registers?1 AnswerThe sound from a mosquito is produced when it vibrates its wings at an average rate of 500 vibrations per second. What is the time period of the vibration? cbse-class8-physics-20151 AnswerRegister renaming is done is pipelined processors-gate-computer science-20121 AnswerSuppose total revenue is rising at a constant rate as more units of a commodity are sold, marginal revenue would be: - CBSE Class 12 Economics 20161 Answerlf at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge? -gate-computer science-20111 AnswerCompare Pentium1,Pentium2 and Pentium3 processor.-Microprocessors-Mumbai University-Sem 5-Dec 2015,Dec 20161 Answern a process, the number of cycles to failure decreases exponentially with an increase in load. At a load of 80 units, it takes 100 cycles for failure. When the load is halved, it takes 10000 cycles for failure. The load for which the failure will hap1 Answer