Explain integer pipeline of Pentium processor
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Explain integer pipeline of Pentium processor.-Microprocessors-Mumbai University-Sem 5-May 2017

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Pentium uses a 5 stage pipeline with the following stages in the pipeline.
1.Prefetch stage - Pentium instructions are variable length and are stored in a prefetch buffer. There is a 256 bit path from instruction cache to the prefetch buffer.
2.Decode 1 stage - In this stage the processor decodes the instruction and finds the opcode and addressing information, check which instructions can be paired for simultaneous execution and participates in branch address prediction.
3.Decode 2 stage - Addresses for memory reference are found in this stage.
4. Execute stage - Data cache fetch or ALU or FPU operation is carried out. Two operations can be carried out at this stage.
5. Write back stage - In this stage the registers and flags are updated on the basis of the results of execution.


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