Explain integer pipeline of Pentium processor

The Eduladder is a community of students, teachers, and programmers just interested to make you pass any exams. So we solve previous year question papers for you.
See Our team
Wondering how we keep quality?
Got unsolved questions?

Ask Questions
10ec62-Micro-processor-->View question

Explain integer pipeline of Pentium processor.-Microprocessors-Mumbai University-Sem 5-May 2017

Related to Pentium processor.


Taged users:


Be first to dislike this question

Talk about thisDelete|Like|Dislike|


Pentium uses a 5 stage pipeline with the following stages in the pipeline.
1.Prefetch stage - Pentium instructions are variable length and are stored in a prefetch buffer. There is a 256 bit path from instruction cache to the prefetch buffer.
2.Decode 1 stage - In this stage the processor decodes the instruction and finds the opcode and addressing information, check which instructions can be paired for simultaneous execution and participates in branch address prediction.
3.Decode 2 stage - Addresses for memory reference are found in this stage.
4. Execute stage - Data cache fetch or ALU or FPU operation is carried out. Two operations can be carried out at this stage.
5. Write back stage - In this stage the registers and flags are updated on the basis of the results of execution.


Be first to like this answer

Be first to dislike this answer
Talk about this|Once you have earned teacher badge you can edit this questionDelete|Like|Dislike|

Can you help us to add better answer here? Please see this

Not the answer you're looking for? Browse other questions from this Question paper or ask your own question.

Join eduladder!